"The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive
new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer
contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the
UCSRnA Register.
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided thatn global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates."
此中断与TXC中断不同,如果在发送一套数据后,发送寄存器会一直空的,这样UDRE中断会一直存在,解决方法就是,在发完后关上UDRE中断。
如果一直产生中断的话,会影响后面的中断的进入。
PS:2011年底,重写飞机上的AVR程序,把以前的usart接收用的TXC中断改为UDRE中断,导致这个问题的发生,被困扰了4天啊。。。基本上都是通宵的。。。。
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